Many modern microprocessors incorporate significant amounts of on-chip memory (such as cache memory), and the present trend toward ever-increasing amounts of on-chip memory have led some industry analysts to forecast that up to 90% of the die area of future processors will be occupied by memory. Different types of memory devices are presently used for the various cache and on-board memory arrays. For example, L1 (Level 1) caches typically use SRAM (Static Random Access Memory) devices, while other caches may use eDRAM (Embedded Dynamic Random Access Memory). Still other memory arrays may use Flash memory, or similar devices. Each type of memory has certain performance, storage, power consumption, and cost characteristics that may be well-suited to one type of application, but not others. These different types of memory devices also often have different device geometries, and are fabricated by different manufacturing processes. For example, SRAM bit-cells require four to six transistors, and are thus relatively costly, but they scale readily to smaller fabrication processes. Flash memory has fewer transistors, but is relatively slow, while DRAM has only one transistor per bit-cell and is relatively fast. Because of size and performance characteristics, DRAM is a popular choice for wide-scale use as stand alone memory, however, these devices also require the use of a capacitor per bit-cell, and the deep trench or stacked structure required for the capacitor produces an aspect ratio that does not scale well to smaller fabrication processes (e.g., beyond 65 nm).
FIG. 1A illustrates an example of a standard DRAM cell with a trench capacitor structure. In FIG. 1A, the DRAM cell 100 comprises a transistor which has a gate 102 that is separated from the substrate 106 by a gate oxide layer 105. Source and drain junctions 104 are formed within silicon substrate 106. The DRAM cell 100 also includes a trench capacitor 110, which extends downward through substrate 106. The capacitor structure 110 can also be a stacked capacitor, which case it would protrude upwards from substrate 106. Although trench technology may provide favorable topographies above the silicon surface, it presents significant challenges below the transistor, and can produce an aspect ratio as large as 90 to 1. This limitation prevents current DRAM devices from exploiting production processes that are much smaller than the current 65 nm or 45 nm technologies. The capacitor structure also imposes significant cost and yield constraints on DRAM manufacturing processes.
One important parameter associated with transistor circuits, such as DRAMs is the feature size of the device. In general, the feature size of the transistor is denoted F, where F corresponds to the minimum gate length that can be produced in the manufacturing process for circuit 100. Thus, for the example circuit of FIG. 1A, the width of gate 102 would define the feature size, F, for circuit 100. Under present manufacturing systems, the bit-cell area for a one-transistor, one-capacitor DRAM device is typically on the order of 2F by 4F, which equals 8F2.
To overcome the fabrication disadvantages of traditional DRAM devices, a new DRAM technology for memory applications has been developed. This technology, referred to as “Z-RAM” consists of a single transistor per bit-cell, with zero capacitors, thus eliminating the deep trench or the complex stacked capacitor. Z-RAM® was developed by, and is a trademark of Innovative Silicon, Inc. of Switzerland. Z-RAM is built on Silicon-on-Insulator (SOI) wafers, and was initially developed for embedded memory applications. In general, various different manufacturing processes can be employed to produce Z-RAM devices. It is desirable to implement a manufacturing process that reduces the size of the memory bit cell, thereby increasing the density of memory cells beyond the current 8F2 DRAM density, and also extends Z-RAM manufacturing processes to standalone memory applications. It is further desirable to provide a manufacturing process that allows DRAM device technology to scale below current manufacturing feature size dimensions, such as 45 nm and below.
It is yet further desirable to utilize a manufacturing process flow for Z-RAM devices that does not affect or alter drastically existing process flows for stand alone memory production for applications in which Z-RAM is used as on-chip memory or other stand alone memory applications.
Disadvantages with present memory cell fabrication processes also extend to the layout of signal lines through arrays of memory cells. FIG. 1B illustrates the bit and word line routing in present capacitor-based DRAM arrays 150. As shown in FIG. 1B, in typical prior art semiconductor lithography systems, DRAM active areas 152 are formed as long rectangular areas that are separated by gaps and staggered from row to row. The active areas 152 comprise the source, drain and gates of the memory transistors, and are parallel to the bit lines 153 of the memory cells. The word lines 162 are polysilicon lines that intersect the active areas 152 to form the transistor gates. The polysilicon gates for the word lines 162 are separated from the active areas at the intersection by a gate oxide layer. The cell layout of FIG. 1B also illustrates capacitor contacts 163 and bit line contact 165. The bit cell area is illustrated by box 154. As shown in array 150, the routing word lines consist of straight line segments and angled segments. Such a routing scheme facilitates the staggered layout of the active areas, but imposes a complication on the lithography process through the requirement of relatively complicated line layouts. Such complications impose practical limits on the degree of scalability of present memory array designs.